发明名称 Decoding apparatus and method therefor
摘要 A decoder decodes input codes, such as Modified Huffman, Modified READ, and Modified Modified READ codes, and includes a zero bit detector which detects the number of consecutive leading zero bits of the input code. An address compressor forms address data by performing a logical operation of data indicating the number of detected zero bits and data excluding the consecutive leading zero bits and the next one bit of the data. A reference table for code conversion is addressed by the formed address data from the address compressor and outputs decoded data corresponding to the input code.
申请公布号 US5751233(A) 申请公布日期 1998.05.12
申请号 US19960644246 申请日期 1996.05.10
申请人 CANON KABUSHIKI KAISHA 发明人 TATENO, TETSUYA;MINAMI, YUJI
分类号 G06T9/00;H03M7/42;H03M7/44;H04N1/419;H04N7/26;(IPC1-7):H03M7/40 主分类号 G06T9/00
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