发明名称 |
Ferroelectric memory devices and method for testing them |
摘要 |
A memory cell comprises a ferroelectric capacitor, first main memory cells are connected to a first bit line, a first reference memory cell is connected to a second bit line, second main memory cells are connected to the second bit line, and a second reference memory cell is connected to the first bit line. When a first operation mode is selected by a control circuit comprising NAND gates and NOR gates, first main memory cells and first reference memory cell are selected, and when a second operation mode is selected, first main memory cells and second main memory cells are selected. Thus, by switching the operation between the two operation modes, a ferroelectric memory device that has stable operation at a low voltage and high integration at a high voltage is provided.
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申请公布号 |
US5751628(A) |
申请公布日期 |
1998.05.12 |
申请号 |
US19960700240 |
申请日期 |
1996.08.20 |
申请人 |
MATSUSHITA ELECTRONICS CORPORATION |
发明人 |
HIRANO, HIROSHIGE;MORIWAKI, NOBUYUKI;NAKAKUMA, TETSUJI;HONDA, TOSHIYUKI;NAKANE, GEORGE |
分类号 |
G11C11/22;(IPC1-7):G11C11/22 |
主分类号 |
G11C11/22 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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