| 摘要 |
A dynamic scannable latch circuit for high-speed memory arrays utilized in high-performance integrated circuit devices, wherein the high-speed memory arrays include data-bearing bitlines. The dynamic scannable latch circuit includes a group of scannable latch circuits for serially reading data from high-speed memory arrays during memory-testing cycles wherein each scannable latch circuit provides a scan output to a scan input of a second or next scannable latch circuit in a series of scannable latch circuits. In addition, the dynamic scannable latch circuit includes sensing and combination circuits for sensing the presence of the data-bearing bitlines and for combining the data-bearing bitlines into a memory array output wherein the sensing and combination circuits are coupled to the group of scannable latch circuits. In addition, the sensing and combination circuits further include NAND circuits integrated into a front end of the dynamic scannable latch circuit. Each NAND circuit includes NAND inputs and a NAND output such that each NAND output is coupled to one of the scannable latch circuits among the group of scannable latch circuits. The integration of the NAND circuit into the front end of the dynamic scannable latch circuit reduces the number of transistors utilized to implement the necessary functions for the memory array output and contributes to minimum delay and proper testability.
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