发明名称 |
Memory implemented error detection and correction code with address parity bits |
摘要 |
A method and apparatus for performing digital signal error detection through the use of a string of received incoming system address bits. The incoming address bits are divided into groups according to whether they contain a high value of "1" or a low value of "0". At least one address parity bit is then generated from each group and used in checking the integrity of data received. |
申请公布号 |
US5751745(A) |
申请公布日期 |
1998.05.12 |
申请号 |
US19970824098 |
申请日期 |
1997.03.25 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CHEN, CHIN-LONG;HSIAO, MU-YUE;LIPPONER, WALTER HEINRICH;SHEN, WILLIAM WU |
分类号 |
G06F11/10;(IPC1-7):G11C29/00 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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