Cache memory with conflict free parallel access

摘要

The cache memory is used in a parallel processing system having a group of N x M processing modules (10), arithmetic logic unit and register file for intermediate storage and address processor and hit/miss recognition logic, which access the cache memory (12) via a memory cross coupling (11). The memory has a number of cell banks (13) R x Q , where R=N+1 and Q=M+1 and each have a number of addressable word memory locations. An input output processor (14) transfers data to and from an external memory. The cache memory provides two-dimensional virtual memory space. Each virtual address space is divided in virtual blocks, representing the smallest common data structure capable of being managed by the cache. Each cell bank is logically segmented into a number of sets and each set is split into several blocks, logical blocks, of data words. To store a virtual block per bank, a logical block is allocated.