| 摘要 |
<p>A clock acquisition subsystem for a data processing system has an interlocked clock multiplexer 100 for acquiring a clock source which is provided as clock signal 102 to the data processing system. Multiplexer 100 has at least two inputs 104 and 106 for clock source signals. Each clock, source signal can be connected to one or more clock sources 110 and 120. Control register 130 specifies which clock source is to be selected by the multiplexer. The multiplexer has an interlocked synchronizer on each clock signal input so that when the multiplexer is switched, output clock signal 102, transitions cleanly from a first clock source to a second clock source without glitches or runt pulses. <IMAGE></p> |
