| 摘要 |
PROBLEM TO BE SOLVED: To provide the system and method for register selection which increases the selecting speed when a memory register is selected according to a constant defined by the sum of two numbers. SOLUTION: A predecoder 41 has a 1st and a 2nd address input. This predecoder 41 processes 1st and 2nd address values (a) and (b) with a width (n) on the 1st and 2nd address inputs to generate 1st, 2nd, 3rd, and 4th predecoded values on corresponding predecoder outputs with corresponding (n+1), (n), (n), and (n-1) widths. A decoding array 43 receives those predecoded values and a decoding array 45 assets one of 2<n+1> register select outputs 15" corresponding to respective registers and does not assert other register select outputs. |
