发明名称 SPURIOUS SIGNAL GENERATING CIRCUIT FOR FOLDING TEST
摘要 PURPOSE:To reduce the scale of hardware monopolized by the test, by operating the tag-in register by encoded information. CONSTITUTION:Tag-in register 16 provided in input/output control device 1 consists of a K-bit flip-flop. Decoder circuit 17 is connected to tag-in register 14, n-bit components of the data line, and P-bit components of the output line of spurious error generating circuit 17 through signal lines. The relation among K bits, n bits, and P bits satisfies K=log2(n+P). If decoder circuit 17 is constituted by the two- input AND gate, n+P gates are sufficient because it decodes K bits. As a result, the number of bits of the flip-flop required in folding tag-in register 16 is reduced considerably.
申请公布号 JPS56153454(A) 申请公布日期 1981.11.27
申请号 JP19800057621 申请日期 1980.04.30
申请人 FUJITSU LTD 发明人 TANIGUCHI HARUMASA
分类号 H04L1/00;G06F11/22;G06F13/00 主分类号 H04L1/00
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