PHASE-LOCKED LOOP CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

PROBLEM TO BE SOLVED: To decrease the circuit scale and to reduce the power consumption by making a phase comparison between a delay signal generated when an input signal makes a plurality of round of a delay stage and the input signal and controlling the delay quantity of the delay stage according to the comparison result. SOLUTION: A clock signal CLK is supplied to the delay stage 2 through a selecting circuit 1 and also supplied to a phase comparator 4. The phase comparator 4 compares the clock signal CLK with the output signal (delay signal INVout ) of the delay stage 2 which is supplied through the selecting circuit 1 and controls an up/down counter 3 according to the comparison result. The delay stage 2 has delay elements in stages and gives delay up to a delay element selected by the up/down counter 3. The selecting circuit 1 is so constituted as to perform switching for delaying the clock signal supplied to the delay stage 2 by the delay stage 2 a specific number of times, i.e., feed the output signal INVout of the delay stage 2 back as an input signal INVin a predetermined number of times.