发明名称 |
IMAGE-PROCESSING UNIT |
摘要 |
PROBLEM TO BE SOLVED: To reduce the capacity of an interlace conversion memory for an MPEG decoder to reproduce dynamic image data. SOLUTION: A processing unit is provided with a frame memory 11 that is provided with five fields each consisting of N sets of slots and with three additional slots. Each slot has a capacity for storing 8 lines worth of image. Four fields among the five fields store a reference frame for motion compensation. The remaining one field and the three additional slots are used for interlace transformation of B picture. A control section 14 is provided with a slot management memory, a write in slot pointer and a readout slot pointer, and the content of the slot management memory is updated in the case of writing in to the frame memory 11 by a bit stream analysis section 12, so that the image output section 13 readouts the frame memory 11 in a correct slot order. |
申请公布号 |
JPH10117356(A) |
申请公布日期 |
1998.05.06 |
申请号 |
JP19970211838 |
申请日期 |
1997.08.06 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
WATABE AKIHIRO;MIYAKOSHI EIJI |
分类号 |
H04N19/50;H03M7/36;H04N19/42;H04N19/423;H04N19/426;H04N19/44;H04N19/503;H04N19/51;H04N19/577;H04N19/59;H04N19/61;H04N19/625;H04N19/85;H04N19/91 |
主分类号 |
H04N19/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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