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发明名称
RE-LAYOUT METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT AND MEDIUM ON WHICH RE-LAYOUT PROGRAM FOR SEMICONDUCTOR INTEGRATED CIRCUIT IS RECORDED
摘要
申请公布号
JPH10116911(A)
申请公布日期
1998.05.06
申请号
JP19960268753
申请日期
1996.10.09
申请人
TOSHIBA CORP
发明人
UEDA TOSHIAKI
分类号
H01L21/82;G06F17/50;(IPC1-7):H01L21/82
主分类号
H01L21/82
代理机构
代理人
主权项
地址
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