发明名称 |
ARITHMETIC CIRCUIT AND FLOATING-POINT MULTIPLICATION DEVICE |
摘要 |
PROBLEM TO BE SOLVED: To speed up the operation of the arithmetic circuit by improving the operation of a data supply means which supplies data used for operation to a computing element. SOLUTION: A flip-flop array 13 supplies data C and data D as the arithmetic result of a 1st adder 11 to a 2nd adder 12. A clock supply means 14 delays an external clock CLK by a delay element and then supplies it to the respective flip-flops of the flip-flop array 13 so that the clock is supplied to the flip-flops on the low-order bit side and relatively early (short delay time) and to the flip-flops on the high-order bit side relatively slowly (long delay time). Consequently, the 2nd adder 12 is supplied with the low-order side bits of the data earlier than the high-order bits, so speed advantages of the low-order bits to the high-order side bits of the data supplied to the flip-flop array 13 are utilized to shorten the operation time. |
申请公布号 |
JPH10116180(A) |
申请公布日期 |
1998.05.06 |
申请号 |
JP19960268283 |
申请日期 |
1996.10.09 |
申请人 |
MATSUSHITA ELECTRIC IND CO LTD |
发明人 |
SEGAWA REIJI |
分类号 |
G06F7/50;G06F7/00;G06F7/487;G06F7/52;G06F7/523;G06F7/527;G11C19/00 |
主分类号 |
G06F7/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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