| 摘要 |
PROBLEM TO BE SOLVED: To complete an asynchronous operation one or several operation before the last operation globally by delaying subsequent transactions by a system interface in a node until an unprocessed coherency activity is completed. SOLUTION: A system interface logic block 62 uses an ignorance signal 70 so as to effectively operate together with ordered restrictions imposed by the output queue/input queue structure of an address controller 52. When a transaction is supplied onto an address bus 58 and the system interface logic block 62 responds to detect the execution of a remote transaction, a logic block 62 asserts the ignorance signal 70. When the ignorance signal 70 is asserted to a certain transaction, the address controller 52 suppresses the storage of the transaction in an input queue 74. Thus, subsequent transactions are delayed from a processor until an unprocessed coherency activity is completed. |
