| 摘要 |
In a Sigma Delta converter, a succession of input signal samples are processed in an iterative manner to provide a succession of output signals and feedback signals, which are matched to the input signal samples over a specified frequency range. Two or more successive iterations are carried out in parallel (37a,37b) so as to provide a sequence of independent outputs (39a,39b) available in parallel. This provision of parallel outputs facilitates an overall increase in the speed of operation of the converter, which is otherwise limited by the maximum available rate of clocking of the converter's filters.<Fig.5>
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