发明名称 SYNCHRONIZER FOR DATA TRANSFER, METHOD AND SYSTEM
摘要 <p>PROBLEM TO BE SOLVED: To transfer a data vector from a 1st domain at a 1st clock rate to a 2nd domain at a 2nd clock rate with respect to an optional frequency or phase relation between the 1st clock rate and the 2nd clock rate. SOLUTION: The synchronizer 50 is provided with a transfer mechanism 52 that transfers data from a 1st clock domain 20 to a 2nd clock domain 22 and a synchronizing mechanism 54 that synchronizes transfer of data from the 1st clock domain 20 to the 2nd clock domain 22 by means of the transfer mechanism. The synchronizing mechanism 54 takes timing in itself based only on the 1st clock rate and the 2nd clock rate without addition of any control signal and the synchronizing mechanism is connected to the transfer mechanism.</p>
申请公布号 JPH10117185(A) 申请公布日期 1998.05.06
申请号 JP19970077525 申请日期 1997.03.28
申请人 FORE SYST INC 发明人 NGUYEN NHIEM T
分类号 G06F15/16;G06F5/06;G06F15/177;H04L7/00;(IPC1-7):H04L7/00 主分类号 G06F15/16
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