| 摘要 |
<p>A synchronous dynamic random access memory device allows an external device to sequentially access read-out data bits in synchronous with a system clock signal (CK), and a column addressing system (151) incorporated in the synchronous dynamic random access memory device forms a plurality of pipeline stages (150c/150d; 150e; DFF4/DFF5) together with an input/ output unit (161) for sequentially supplying data bits to a data port (DP10) in response to a column address (DC1) internally incremented in synchronism with the system clock signal, thereby propagating the data bits through a single data bus (161a). <IMAGE></p> |
