发明名称 |
Address generation unit with segmented addresses in a microprocessor |
摘要 |
A processor having an address generation unit (AGU) for generating an address corresponding to an entry that is to be fetched. The AGU includes a segment register file for storing address segments, and a circuit for rearranging noncontiguous base and limit bit positions of a first address segment in order to generate a second address segment having all base and limit bits in a contiguous order. The AGU further includes a circuit for executing a single microinstruction to perform read and write operations on a selected field of the second address segments stored in the segment register file.
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申请公布号 |
US5749084(A) |
申请公布日期 |
1998.05.05 |
申请号 |
US19960634092 |
申请日期 |
1996.04.17 |
申请人 |
INTEL CORPORATION |
发明人 |
HUCK, KAMLA P.;RODGERS, SCOTT D.;GLEW, ANDREW F. |
分类号 |
G06F9/34;G06F12/02;G06F12/08;G06F12/10;(IPC1-7):G06F12/02;G06F12/06 |
主分类号 |
G06F9/34 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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