| 摘要 |
In a telecommunication system having multiple timing subsystems receiving and distributing redundant timing signals, there is provided a circuitry (8, 100) for aligning first and second redundant timing signals (10, 12, 110, 112) and switching therebetween. The circuitry includes first and second phase-locked loops (18, 20, 118, 120) for receiving first and second redundant timing signals (10, 12, 110, 112), respectively, and multiplying the frequency of first and second redundant timing signals (10, 12, 110, 112) by a factor of N. The circuitry further includes a selecting and switching circuitry (34, 134) for receiving the multiplied first and second redundant timing signals (22, 23, 122, 124) and designating one as ACTIVE and the other as INACTIVE, and providing the ACTIVE timing signal as an output timing reference signal (54, 154). The selecting and switching circuitry further operating to switch the ACTIVE and INACTIVE timing signal designations and output timing reference signal in response to detecting a fault or a clock switching command. The ACTIVE timing signal is provided to a phase integrator (40, 140), which integrates phase transients out of the ACTIVE timing signal to avoid jitter in the output timing reference (54, 154).
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