Advanced program verify for page mode flash memory

摘要

PCT No. PCT/US95/00077 Sec. 371 Date Mar. 4, 1996 Sec. 102(e) Date Mar. 4, 1996 PCT Filed Jan. 5, 1995 PCT Pub. No. WO96/21227 PCT Pub. Date Jul. 11, 1996Flash EEPROM cell and array designs, and methods for programming the same result in efficient and accurate programming of a flash EEPROM chip. The flash EEPROM chip comprises a memory array including at least M rows and N columns of flash EEPROM cells. M word lines are each coupled to the flash EEPROM cells in one of the M rows of flash EEPROM cells. A plurality of bit lines are each coupled to the flash EEPROM cells in one of the N columns of flash EEPROM cells. A page buffer coupled to the plurality of bit lines supplies input data to N columns of flash EEPROM cells. Write control circuitry supplies programming voltages for programming input data to the flash EEPROM cells in response to the input data stored in the data input buffer. Verify circuitry automatically verifies programming of the page by resetting bits in the page buffer for each cell which passes.