Line data architecture and bus interface circuits and methods for dual-edge clocking of data to bus-linked limited capacity devices

摘要

A data system architecture and interface circuits permit slow devices having limited signal capacities to launch and receive information from a central bus. Data is clocked onto the bus with a master circuit at the leading and trailing edges of the bus clock so that portions of a large multibit signal are launched without having to wait for the initiation of a next clock cycle. Accordingly, data portions are launched during both leading and trailing edges of the clock signal. In the case of a simple bus device not able to accommodate inclusion of a slave interface circuit, the received signal packet is provided in adapted form anticipating that only a second half portion of the signal packet will actually be registered as received.