发明名称 |
Apparatus for detecting and correcting cyclic redundancy check errors |
摘要 |
A cyclic redundancy check (CRC) circuit for detecting and correcting errors in a data stream uses a decoder and a serial-to-parallel buffer to shorten arithmetic operation time. The CRC circuit includes a first gate for switching a serial input data stream into a syndrome register section, and a buffer register for converting the serial input data to a parallel data. The syndrome register section forms redundancies for input data stream. An OR gate receives data from the syndrome register section to enable a decoder if the syndrome register section detects an error in the data stream. The decoder decodes the output from the syndrome register section. The output of the decoder is exclusively-ORed with the input data in the parallel shift register. A latch circuit thereafter outputs a corrected serial data stream.
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申请公布号 |
US5748652(A) |
申请公布日期 |
1998.05.05 |
申请号 |
US19960664002 |
申请日期 |
1996.06.14 |
申请人 |
HYUNDAI ELECTRONICS IND. CO., LTD. |
发明人 |
KIM, JIN-TAE |
分类号 |
G06F11/10;H03M13/00;H03M13/09;(IPC1-7):G06F11/10 |
主分类号 |
G06F11/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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