| 摘要 |
A bit pattern detector for detecting a bit pattern in a parallel bitstream input includes left and right matching units for detecting bits in the bitstream input that match the bit pattern. The left matching unit outputs a plurality of signals to an adder, a multiplexer, and a pattern detector, depending on whether and how many matching bits are detected in the bitstream input. The right matching unit also outputs a signal to the adder. The pattern detector outputs a detection signal depending on the input from the left matching unit and the adder, and also outputs a control signal to the multiplexer. The multiplexer selects and outputs a signal from amongst the signals received thereby from the left matching unit and a size signal corresponding to a size of the bitstream input. The detector also may include a bit pattern register which stores the bit pattern and provides it to the left and right matching units, and a bit number register for storing the signal received from the right matching unit.
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