| 摘要 |
A scalable architecture MPEG2 compliant digital video encoder system having an I-frame video encoder module with a Discrete Cosine Transform processor, a quantization unit, a variable length encoder, a FIFO buffer, and a compressed store interface, for generating an I-frame containing bitstream. The system also includes a second processor element with a reference memory interface, motion estimation and compensation capability, inverse quantization, and inverse discrete cosine transformation, and motion compensation means; and at least one third processor element for motion estimation. According to the invention, the difference data between the current macroblock and the reference macroblock is stored, which may be of different formats, is storted in memory in a common format by blocking bits in an address counter of the memory.
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