Cache memory system for dynamically altering single cache memory line as either branch target entry or prefetch instruction queue based upon instruction sequence

摘要

A processor with a branch target cache (BTC) and multiple instruction prefetch storage circuits. A control mechanism allows the fetching of instructions to be transferred from a first prefetch storage circuit to a second prefetch storage circuit which contains branch target instruction bytes. The control is transferred based on a prediction of whether the branch will be taken using history bits associated with the branch instruction. If the processor later determines that the branch is mispredicted, the execution of instructions resumes from the first prefetch storage circuit.