发明名称 SWITCHED CAPACITOR ADDER
摘要 PURPOSE:To perform LSI-implementation by arranging capacitors which each have switches on both ends at >=2 input terminals and one terminal of an operational amplifier, and controlling the opening and closing operations of a switch according to a coefficient of binary number. CONSTITUTION:An input signal phis from an input terminal Vin1 is held by a sample holding circuit 1. Switches 2 and 3 are connected to the ground side at the timing of phi2'', and the input signal is transferred to a capacitor CD through a capacitor CA. Further, the switches 2 and 3 are connected to the side of the operational amplifier 9 at the timing of phi1'', and the charge in the capacitor CA is discharged. A weight coefficient circuit 4 is in binary mode, and turns on the phi1'' at the time of ''1'' and cuts off at the time of ''0''. A capacitor CE has the same capacity value with the capacitor CD, and is grounded at the timing of phi1 and connected to the capacitor CD in parallel at the timing of phi2 to reduce the charge in the capacitor CD to half at every timing phi2. Consequently, the ratio of the capacitors in use may be small, so the LSI-implementation is facilitated.
申请公布号 JPS59231677(A) 申请公布日期 1984.12.26
申请号 JP19830107174 申请日期 1983.06.15
申请人 FUJITSU KK 发明人 KANEKO KAZUHIRO;KATOU SEIJI
分类号 G06G7/14;(IPC1-7):G06G7/14 主分类号 G06G7/14
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