发明名称 DETECTION SYSTEM FOR CLOCK BREAK
摘要 PURPOSE:To detect a break of a long-period clock by summing up pulses generated by plural monostable multivibrators. CONSTITUTION:The clock T2 having a long period as shown by (d) is inputted to an input terminal 1 and allows a monostable multivibrator 5-1 to operate to generate a pulse (e) with pulse width T'2. The pulse (e) is inputted to an OR gate circuit 6 and drives a next monostable multivibrator 5-2 with the trailing edge to generate a pulse (f), which drives a next monostable multivibrator 5-3 similarly; and the output of the monostable multivibrator drives a next monostable multivibrator 5-4 and is also inputted to the OR gate 6. Similarly, monostable multivibrators 5-3 and 5-4 are driven in order to input their output pulses (g) and (h) to the gate 6. Consequently, the gate 6 outputs a signal (i) with a level ''1''. If the clock T2 is broken at a point P', the trailing edge i-1 of the output (i) of the gate 6 is held by a trailing-stage latch circuit 4 to decide on the break of the clock.
申请公布号 JPS6083417(A) 申请公布日期 1985.05.11
申请号 JP19830191603 申请日期 1983.10.13
申请人 FUJITSU KK 发明人 IKEDA TOSHIO;FUJII YUUZOU;IDEGUCHI HIROTOMO
分类号 H03K5/19;(IPC1-7):H03K5/19 主分类号 H03K5/19
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