| 摘要 |
<p>A mixed signal phase locked loop (100), optimized for fast settling and low noise, includes a digital wide range delay line oscillator (200). When first activated, the loop (100) calibrates the digital delay line oscillator (200) to its nominal delay characteristics using a reference delay line (300). After achieving nominal delay, the oscillator (200) is locked to a desired reference frequency or a submultiple thereof. After achieving lock, the loop (100) performs synchronous data recovery by locking to an incoming data stream, instead of the reference frequency.</p> |
