发明名称 |
MIXED SIGNAL PHASE LOCKED LOOP |
摘要 |
A mixed signal phase locked loop (100), optimized for fast settling and low noise, includes a digital wide range delay line oscillator (200). When first activated, the loop (100) calibrates the digital delay line oscillator (200) to its nominal delay characteristics using a reference delay line (300). After achieving nominal delay, the oscillator (200) is locked to a desired reference frequency or a submultiple thereof. After achieving lock, the loop (100) performs synchronous data recovery by locking to an incoming data stream, instead of the reference frequency.
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申请公布号 |
WO9818207(A1) |
申请公布日期 |
1998.04.30 |
申请号 |
WO1997US18861 |
申请日期 |
1997.10.23 |
申请人 |
QUALITY SEMICONDUCTOR, INC. |
发明人 |
DICKE, CURTIS, J.;WOLOSEWICZ, JACK |
分类号 |
H03L7/099;H03L7/10;(IPC1-7):H03L7/099 |
主分类号 |
H03L7/099 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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