| 摘要 |
PURPOSE:To avoid a case where data are sent to a circuit by mistake by inhibiting the transmission of the transmission enable signal although a transmission request is given from a transmitter/receiver and stopping immediately the transmission of data when the transmission is through with the data on the last block. CONSTITUTION:A DMA (direct memory access) controller 1 delivers a block transfer end signal to a set clock control circuit 4 via a signal line 11 after confirming the end of transfer of the data on a block. The circuit 4 secures the synchronism with a clock and applies a block control signal to a clock control circuit 3 via a signal line 12. The designation of the last block is set to the circuit 3 via a signal line 14 connected to a bit of a common bus 7. No start request signal is sent to the controller 1 even though a transmission request signal is received from a receiver 2 in case the block control signals are received by the prescribed frequency after the last block designation is set. Thus no transmission enable signal is sent to the receiver 2 from the controller 1 and therefore the receiver 2 sends no data to a circuit 8. |
