发明名称 FIELD EFFECT TRANSISTOR AND FABRICATION PROCESS THEREOF
摘要 Using a mask opening a gate region, an undoped GaAs layer is selectively etched with respect to an undoped Al0.2Ga0.8As layer by dry etching with introducing a mixture gas of a chloride gas containing only chlorine and a fluoride gas containing only fluorine (e.g. BCl3 + SF6 or so forth). By about 100% over-etching is performed for the undoped GaAs layer, etching (side etching) propagates in transverse direction of the undoped GaAs layer. With using the mask, a gate electrode of WSi is formed. Thus, a gap in a width of about 20 nm is formed by etching in the transverse direction on the drain side of the gate electrode. By this, a hetero junction FET having reduced fluctuation of characteristics of an FET, such as a threshold value, lower a rising voltage and higher breakdown characteristics.
申请公布号 CA2219598(A1) 申请公布日期 1998.04.30
申请号 CA19972219598 申请日期 1997.10.29
申请人 NEC CORPORATION 发明人 IWATA, NAOTAKA;YAMAGUCHI, KEIKO
分类号 H01L29/41;H01L21/285;H01L21/306;H01L21/335;H01L21/338;H01L29/812;(IPC1-7):H01L29/772 主分类号 H01L29/41
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