A SUM OF THE ABSOLUTE VALUES GENERATOR

摘要

An apparatus (10) for processing sum of the absolute differences (SAD) is disclosed. A novel circuit is disclosed which eliminates the requirement of taking the absolute value of intermediate partial sum results. The absolute value function is only needed after the final summation stage (70). Subtraction units (12) take the difference between each pair of values to be processed. Each summation unit (20) performs an addition on its two inputs while preserving the magnitude of their sum. Depending on the sign of one of the inputs, the two inputs are either added to each other or subtracted from each other. The sign bit of both inputs are checked in order to determine to add or subtract.