Method and system for soft programming algorithm

摘要

PCT No. PCT/US95/15051 Sec. 371 Date Mar. 21, 1996 Sec. 102(e) Date Mar. 21, 1996 PCT Filed Nov. 17, 1995 PCT Pub. No. WO97/19452 PCT Pub. Date May 29, 1997A floating gate memory device which includes control circuits to generate a repair pulse to repair over-erased cells so they may be repaired block-by-block. This invention includes repairing the cells by applying a repair pulse to the cell's bit line while maintaining the word line voltage above ground. In a different embodiment, the word line voltage is maintained at two different voltage levels above ground. In the first stage, the word line voltage is maintained between approximately 0.1 volts and 0.2 volts for approximately 100 ms while the repair pulse is applied. In the second stage, the word line voltage is maintained between approximately 0.4 volts and 0.5 volts for approximately 100 ms while the repair pulse is applied.