发明名称 |
FPLL with third multiplier in an AC path in the FPLL |
摘要 |
A FPLL has first second and third multipliers with the first multiplier supplying demodulated signals to a limiter and the second multiplier supplying signals to the loop filter. A VCO and phase shift circuit supply quadrature signals to the first multiplier and to the third multiplier which is relocated to an AC path in the loop to avoid the effects of offsets due to stray DC voltages and currents. The limiter output is applied to the third multiplier. The third multiplier supplies its output to the second multiplier. An integrated circuit embodiment using an exclusive OR gate as the third multiplier is also shown.
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申请公布号 |
US5745004(A) |
申请公布日期 |
1998.04.28 |
申请号 |
US19960678902 |
申请日期 |
1996.07.12 |
申请人 |
ZENITH ELECTRONICS CORPORATION |
发明人 |
MYCYNEK, VICTOR;SGRIGNOLI, GARY |
分类号 |
H03L7/087;H04L27/06;(IPC1-7):H03L7/087;H04L27/227 |
主分类号 |
H03L7/087 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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