| 摘要 |
<p>PROBLEM TO BE SOLVED: To continue a stable operation even when a supplied clock is distorted in the process of a state transition by validating the input of an asynchronous set or an asynchronous reset so as to operate a synchronization flip-flop asynchronously and changing forcibly a latched content to a state to be substantially set. SOLUTION: In this control circuit, a reset signal is applied simultaneously to an asynchronous set terminal and an asynchronous reset so terminal of two D flip-flop circuits A12, A13 so as to set them forcibly to '0', '1' respectively. Thus, even when there is any distortion in a low speed clock supplied from a frame counter to the control circuit due to a reset signal outputted when the operating state transits from a hunting state to a backward protection state, the state of the D flip-flop circuits A12, A13 is forcibly reset or set by the reset signal so as to transit the control circuit surely to a state to be substantially set.</p> |
