发明名称
摘要 PURPOSE:To achieve effect for suppressing voltage ripples caused by multiplexing positively by providing a bias signal correcting circuit for decreasing the absolute value of the bias signal upon increase thereof. CONSTITUTION:Output from a bias signal generator 19g is corrected through a bias signal correcting circuit 19h and then delivered to comparators 19d, 19e for second inverters 7, 8. In this regard, correcting function is a function of bias signal V1* of a first inverter 6 and takes a value of 1 when V1*=0 and increases monotonously as 1V1* increases. Consequently, corrected bias signal V2** has a trend of monotonous increase. When the inverter is driven based on the outputted bias signal V2**, bias signal for the second inverters 7, 8 is also increased through correction thus increasing pulse width of output voltage and suppressing ripples in the combined voltage significantly. Consequently, the effect for suppressing ripples caused by multiplexing is exhibited positively even when the bias signal is increased.
申请公布号 JP2746010(B2) 申请公布日期 1998.04.28
申请号 JP19920279749 申请日期 1992.10.19
申请人 发明人
分类号 H02M7/48;H02M7/497;H02P27/06 主分类号 H02M7/48
代理机构 代理人
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