发明名称 |
Digital locked loop |
摘要 |
A digital locked loop uses feedback to maintain an output digital signal in a specific digital relationship with a reference digital signal. The digital locked loop can lock an input digital signal according to a reference digital signal by using a digital counter, a resister and an arithmetic logic circuit instead of a phase locked loop and a frequency locked loop in motor drive integrated circuit for permanent magnetic brushless DC multi-phase motor drive applications. The circuit is designed not to use a voltage-controlled oscillator VCO and can be extended to broader applications such as digital data communications, digital image processing, and in the multi-media industry.
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申请公布号 |
US5744928(A) |
申请公布日期 |
1998.04.28 |
申请号 |
US19960638745 |
申请日期 |
1996.04.29 |
申请人 |
SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
TANG, SHI-MING;LEE, SANG-YONG |
分类号 |
G05B11/06;H02P6/06;H02P23/00;H02P29/00;H03L7/00;H03L7/06;H03L7/181;H04L7/033;(IPC1-7):H02P7/00 |
主分类号 |
G05B11/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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