| 摘要 |
Method and apparatus for improved detection of multiple-bit errors which occur within a single memory circuits. In one embodiment, a computer system is described which includes a main computer and a memory system. The memory system includes a plurality of memory circuits, at least one of the plurality of memory circuits having a data interface more than two bits wide. Also included is a multiple-bit-error-detect (MBED) circuit, wherein bits from the plurality of memory circuits are coupled to the MBED circuit in an order which causes the MBED circuit to preferentially detect multiple-bit errors which occur on the data interface of any single one of the plurality of memory circuits. In another embodiment, the method comprises the steps of: a) providing an initial bit-connection order between the plurality of memory circuits and the error-detection circuit; b) testing each of the predetermined set of possible multi-bit error conditions; c) determining whether the error-detection circuit provides (1) an erroneous no-error/single-bit-error indication or (2) a non-erroneous multiple-bit-error indication for each one of the predetermined set of possible multi-bit error conditions; and d) based on a number of erroneous indications or non-erroneous indications determined in step c), either: re-ordering the bit-connection order and reexecuting step b), or providing the bit-connection order as an output. In one such embodiment this method is used wherein the step of re-ordering comprises the step of shifting at least one bit connection from the first memory circuit to the second memory circuit.
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