发明名称 |
Process or renders repeat operation instructions non-cacheable |
摘要 |
A Central Processing Unit is provided having an instruction processor for determining CPU instruction types. An instruction detector is included in the CPU for detecting whether a determined instruction is a non-cacheable repeat operation instruction. The CPU has an execution unit for executing instruction and for outputting a CPU signal indicating whether data associated with an instruction is cacheable.
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申请公布号 |
US5745728(A) |
申请公布日期 |
1998.04.28 |
申请号 |
US19950572233 |
申请日期 |
1995.12.13 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
GENDUSO, THOMAS BASILIO;VANDERSLICE, EDWARD ROBERT |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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