发明名称 |
Error correcting decoder |
摘要 |
An error correcting decoder includes a flag memory (20) which stores a flag indicative of a success of an error correction for a bit. When a column direction error correction is to be performed, if a flag for a bit indicates a success, no error correction is performed for the bit. That is, an output of a majority logic circuit (78) is forcedly made invalid. In performing the column direction error correction, if the number of success packets in a first-time row direction error correction is smaller than a predetermined value and if the number of bits corrected by the column direction error correction becomes equal to or larger than a predetermined number, it is deemed as that the column direction error correction is unsuccessful. In performing a second-time row direction error correction, when a threshold value is equal to or larger than a predetermined value, the majority logic circuit determines with referring to a result of the column direction error correction, but without referring to the result when the threshold value is smaller than the predetermined value.
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申请公布号 |
US5745506(A) |
申请公布日期 |
1998.04.28 |
申请号 |
US19950449916 |
申请日期 |
1995.05.25 |
申请人 |
SANYO ELECTRIC CO., LTD.;NIPPON HOSO KYOKAI |
发明人 |
YAMASHITA, SYUGO;TOMIDA, YOSHIKAZU;TAKADA, MASAYUKI;KURODA, TORU;ISOBE, TADASHI;YAMADA, OSAMU |
分类号 |
H03M13/00;H04J1/00;H04L1/00;(IPC1-7):H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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