| 摘要 |
<p>PURPOSE:To prevent a malfunction by inhibiting an operation of an oscillation stabilizing timer by a level of an external input during a period in which an oscillation is unstable, and starting the timer after the level of the external input has been inverted. CONSTITUTION:In order that an oscillator 100 releases a stop mode which has stopped an oscillation, an external input signal 210 becomes a second logic level from a first logic level, and thereafter, until it becomes the first logic level again, an operation of an oscillation stabilizing timer 104 is inhibited. Subsequently, after a level of an external input has been inverted, the timer 104 is started. In such a way, an oscillation stable time as per a design value is obtained, and also, the bit length of the timer contained as a hardware can be curtailed, and a malfunction can be prevented.</p> |
