| 摘要 |
A steering circuit for use with a phase locked loop (PLL) includes a D-type flip flop (72) having a data and clock input terminals and first and second output terminals at which are produced complementary logic output signals, and first (80, 82, 84, 86) and second (88, 90) current sources having inputs respectively coupled to the first and second outputs of the flip flop and outputs connected to an output (92) of the steering circuit. The steering circuit is responsive to error beat note signals generated by the PLL for either sourcing or sinking first and second currents at the output thereof depending whether the input signal frequency to the PLL is greater or less than the oscillation frequency of the voltage controlled oscillator (VCO) (22) of the PLL. The output of the steering circuit is connected to the control input terminal of the VCO such that the latter is driven to lock. |
