发明名称 SCANNING TEST METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To easily determine whether a semiconductor integrated circuit is normally operating or not by using the latch data of a flip-flop(FF). SOLUTION: After a semiconductor integrated circuit is operated to latch data in plural FF1s contained in it, the circuit is changed in a testing mode connection. In a testing mode connection, for example, scanning paths 101 to 10m where plural stages of FFs are connected and scanning paths 111 to 11m corresponding to them are constructed. When expected values of latch data for one set of scanning paths 101 to 10m are written in another set of scanning paths 111 to 11m and they are shifted, exclusive logical sum circuits 121 to 12m successively compare the latch data with expected values, and a logical sum circuit 13 successively outputs data indicating whether the semiconductor integrated circuit normally operates. As long as the latch data matches its expected value, the logical sum circuit 13 outputs '0'.
申请公布号 JPH10111346(A) 申请公布日期 1998.04.28
申请号 JP19960266364 申请日期 1996.10.07
申请人 OKI ELECTRIC IND CO LTD 发明人 NAKAMURA KIYOUTAROU
分类号 G01R31/28;G01R31/3185;G06F11/22 主分类号 G01R31/28
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