| 摘要 |
<p>PROBLEM TO BE SOLVED: To optionally adjust entire clock skew without adding an unnecessary delay circuit in constructing a system by incorporating a hard mega cell of which function verification is preliminarily performed by providing a hard mega cell row with a sub clock buffer that adjusts clock skew. SOLUTION: Clock which is inputted by a system clock input terminal 8 is inputted from a clock line 9 to each clock through a main clock buffer 6. A RISC processor 2 and peripheral hard mega cells 3 to 5 are preliminarily and separately undergone function verification, and transistors, etc., are already and optimally arranged. Each hard mega cell 3 to 5 and a standard cell block 6 are provided with a sub clock buffer (e.g. 18, etc.,). One or a plurality of sub clock buffers are preliminary arranged in each row so as to adjust clock skew optionally. Thereby, skew adjustment can be performed in each row.</p> |
