| 摘要 |
<p>PROBLEM TO BE SOLVED: To set a stop level for a clock signal which minimizes the power consumption of a control circuit part for any kind of control circuit part without increasing the cost or circuit scale. SOLUTION: This device is provided with a clock stop level setting means 4 which sets the stop level for the optimum clock signal for maintaining the low power consumption state of the control circuit 21 which operates with the inputted clock signal and enters the low power consumption state when the clock signal is stopped, a storage means 5 which stores the set stop level for the clock signal, and clock signal control means 6 and 7 which sets clock signals from clock generating means 2 and 3 to the stop level stored in the storage means when the said control circuit part is in the low power consumption state; when the control circuit part such as a CPU and an LSI is in the low power consumption state, the clock signal is stopped with the stop level matching the control circuit part.</p> |
