| 摘要 |
PROBLEM TO BE SOLVED: To simultaneously carry out read operation and write operation to different memory banks while keeping a one-port structure, by determining the number of memory cells of a plurality of memory banks. SOLUTION: A read-enable clock signal and a write-enable clock signal are set to the same clock frequency. Supposing that the number of memories of an SRAM is N and every memory cell can be serially accessed, accessing to data is sequentially carried out from the first memory cell to an Nth memory cell while both read and write enable clock signals are at a high level. The write enable clock signal rises earlier than the read enable clock signal, and therefore a read operation is not executed when data are written to the first memory cell. A collision of read and write operations is not brought about. At the write time to an Ath cell, data banks are always separated by different paths in accordance with a length of A memory cells of an area 10. |
