| 摘要 |
PROBLEM TO BE SOLVED: To omit trouble of matching a clock frequency between a master side and a slave side by synthesizing a data signal and a clock signal into a plurality of level signals with a different level. SOLUTION: When a transfer clock 117 from a control circuit 101 in a master side data communication section 1 is at logical H, a PMOS transistor(TR) 107 is conductive to boost a level of a transmission reception serial signal 121 to a high level 120. A register 109 converts transmission data 122 from the control circuit 101 into a serial signal 124. When the transfer clock 117 and the serial signal 124 are both at logical L, an NMOS TR 111 is turned on through a NOR gate 110 to set the transmission reception serial signal 121 to logical L. When the transfer clock 117 or a serial signal 124 is logical H, the NMOS TR 111 is turned out to boost the transmission reception serial signal 121 to a middle level 126. |
