发明名称 HIGH EFFICIENT ENCODING AND DECODING SYSTEM
摘要 A high efficient encoding/decoding system has processor for processing a small block having at least one collection of blocks as an encoding unit of input data, and a macro block having a macro block length data for indicating the length of the macro block itself in its head position and at least one of the small blocks. The collection of blocks in the small block includes a first passage for a variable length data having at least one collection of data obtained by performing a variable length encoding for every block of encoding unit on the input data, header information associated with the variable length data and a small block length data for indicating the length of the small block itself, a second passage for an adjustment bit data and a length data indicating the length of the adjustment bit data itself, and a third passage for a correction directing signal, thus for transmitting a data for selecting at least one of the three passages by embedding the selecting data in a coefficient based on an encoding characteristics of the variable length data. <IMAGE>
申请公布号 KR0134871(B1) 申请公布日期 1998.04.22
申请号 KR19930013422 申请日期 1993.07.16
申请人 TOSHIBA KK. 发明人 KENJI, SHIMODA
分类号 H04N7/26;H04N7/30;H04N7/50;H04N7/52;H04N9/804;(IPC1-7):H04N7/24;H04N5/78 主分类号 H04N7/26
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