| 摘要 |
<p>A semiconductor memory device (100) is associated with peripheral logic gates (101) producing at least an address signal (ADD) representative of an address, a write-in enable signal (WE) and an input data signal (Din) indicative of a piece of data information, and said peripheral logic gates selectively enters an usual mode of operation and a scan-path diagnostic mode of operation, wherein the semiconductor memory device comprises a memory cell array (100a) having a plurality of memory cells (MC11/MCm1/MC1n/MCmn) each having an address and memorizing a piece of data information, and peripheral circuits having a write-in controlling circuit (100i) supplying a write-in controlling signal for allowing a piece of data information to be memorized in one of said memory cells designated by said address signal and a prohibiting circuit (100h) operative to prohibit said write-in controlling circuit from supplying said write-in controlling signal in said diagnostic mode of operation, thereby preventing pieces of data information memorized in the memory cell array from destruction.</p> |
