Improvements in or relating to microprocessor integrated circuits

摘要

A microprocessor and system including a floating-point unit (FPU) (31) for performing floating-point division are disclosed. According to the preferred embodiment of the invention, FPU (31) includes a divisor reciprocal ROM (55a) and circuitry (61) for rapidly generating the logical complement of a divisor reciprocal estimate. The divisor reciprocal estimate is multiplied, by way of a multiplier array in FPU (31), with the dividend operand to generate an initial quotient estimate. The multiplier array is constructed to have additional bits beyond those required to express the result, to provide adequate accuracy in the results. Successive iterations are performed by FPU (31) to refine the estimate of the quotient by using a reciprocal adjustment factor produced by the logical complement of a divisor adjustment factor. Significant performance improvement is obtained by using the logical complement of the divisor adjustment factor, as compared with full precision subtraction involved in the two's complement of the factor as in conventional circuitry and methods. <IMAGE>