| 摘要 |
A microprocessor core operating on instructions in a dual six-stage pipeline. Instructions are fetched and decoded by an instruction scheduling unit which includes a queuing stage for facilitating conditional branch operations. Instructions can be executed in five execution units including a load/store/add unit, an ALU unit, a shift/multiply unit, a branch unit, and a coprocessor which interfaces with the microprocessor core. Exceptions are handled by the coprocessor which includes a plurality of registers and a multiple entry translation lookaside buffer and an exception program counter. When an exception is detected the coprocessor loads the exception program counter with a restart address where execution can resume after the exception is serviced, the plurality of registers being used during the exception processing. One of the registers is a circulate mask register which is used by the coprocessor in executing an Add with Circular Mask instruction in which an immediate field of the instruction is sign-extended and added to the contents of a general register, the result being masked with the extended value in the circular mask register. |
